Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

3.8. Addition of Timing Constraints

A Custom Platform must apply the correct timing constraints to the Intel® Quartus® Prime project. In the Intel® Arria® 10 FPGA Development Kit Reference Platform, the top.sdc file contains all timing constraints applicable before IP instantiation in Platform Designer. The top_post.sdc file contains timing constraints applicable after Platform Designer generation is run.

The order of the application of time constraints is based on the order of appearance of the top.sdc and top_post.sdc files in the top.qsf file.

One noteworthy constraint in the a10_ref Reference Platform is the multicycle constraint for the kernel reset in the top_post.sdc file. Using global routing saves routing resources and provides more balanced skew. However, the delay across the global route might cause recovery timing issues that limit kernel clock speed. Therefore, it is necessary to include a multicycle path on the global reset signal.