Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

3.1.9. Cable Autodetect

If partial reconfiguration (PR) cannot be used or fails to reconfigure the OpenCL kernel-related partition of the design, an attempt is made to do a full JTAG programming over the Intel FPGA Download Cable (formerly USB-Blaster).

The Intel® Arria® 10 GX FPGA Development Kit Reference Platform automatically tries to detect the cable by default when programming the FPGA via the Intel FPGA Download Cable.

You can set the ACL_PCIE_JTAG_CABLE or ACL_PCIE_JTAG_DEVICE_INDEX environment variables to disable the auto-detect feature and use values that you define.

Cable autodetect is useful when you have multiple devices connected to a single host and PR cannot be used to program the FPGA.

The memory-mapped device (MMD) uses in-system sources and probes to identify the cable connected to the target board. You must instantiate the cade_id register block and connect it to Bar 4 with the correct address map. You must also instantiate board_in_system_sources_probes_cade_id, which is an in-system sources and probe component, and connect it to cade_id register.

The MMD must be updated to take in the relevant changes. Add the scripts/find_jtag_cable.tcl script to your custom platform.

When the FPGA is being programmed via the Intel FPGA Download Cable, the MMD invokes quartus_stp to execute the find_jtag_cable.tcl script. The script identifies the cable and index number which is then used to program the FPGA through the quartus_pgm command.