Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Document Table of Contents

3.4. Intel® Arria® 10 FPGA System Design

To integrate all components, close timing, and deliver a post-fit netlist that functions in the hardware, you must first address several additional FPGA design complexities.

Examples of design complexities:

  • Designing a robust reset sequence
  • Establishing a design floorplan
  • Managing global routing
  • Pipelining

Optimizations of these design complexities occur in tandem with one another to meet timing and board hardware optimization requirements.

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