Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Public
Document Table of Contents

3.1.10.2. Host Channel Top Connection to PCIe* DMA

In addition to the ports connected in DMA section, by disabling Instantiate internal descriptor controller setting on Intel® Arria® 10 Hard IP for PCI Express* , ReadDCS, WrDCS, rd_ast_rx, wr_ast_rx, RdDmaRx and WrDmaRx ports are exposed on the IP.

These ports must be connected to the DMA descriptor controller in the host channel IP.

Base address offset must match the address mentioned in the board.qsys file, since these addresses are used by the internal descriptor controller of a10gx board variant.

You need to make the following connections:
  • On acl_hostchannel_top IP, rd_dma and wr_dma ports are used to receive and send data to DMA. These ports must be connected to the corresponding ports on PCIe* IP with base address offset matching in the hw_host_channel.h header file.
  • The cra port must be connected to the host_ctrl.
  • The msi_interface port must be connected to Intel® Arria® 10 Hard IP for PCI Express* , and the msi_interface_out must be connected to the msi_interface port of the pcie_irq.