Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

3.3.3.2. Main Clock Group

The main clock group consists of a PLL, dividers, and clock gating. The clocks in the main clock group are derived from the main PLL. The main PLL is always sourced from the HPS_CLK1 pin of the device.

Table 9.  Main PLL Output Assignments

PLL

Output Counter

Clock Name

Frequency

Phase Shift Control

Main

C0

mpu_base_clk

osc1_clk to varies

7

No

C1

main_base_clk

osc1_clk to varies

7

No

C2

dbg_base_clk

osc1_clk/4 to mpu_base_clk/2

No

C3

main_qspi_base_clk

Up to 432 MHz

No

C4

main_nand_sdmmc_base_clk

Up to 250 MHz for the NAND flash controller and up to 200 MHz for the SD/MMC controller

No

C5

cfg_h2f_user0_base_clk

osc1_clk to 125 MHz for driving configuration and 100 MHz for the user clock

No

The counter outputs from the main PLL can have their frequency further divided by programmable dividers external to the PLL. Transitions to a different divide value occur on the fastest output clock, one clock cycle prior to the slowest clock’s rising edge. For example the clock transitions on cycle 15 of the divide‑by‑16 divider for the main C2 output and cycle 3 of the divide‑by‑4 divider for the main C0 output.

The following figure shows how each counter output from the main PLL can have its frequency further divided by programmable post‑PLL dividers. Green-colored clock gating logic is directly controlled by software writing to a register. Orange-colored clock gating logic is controlled by hardware. Orange-colored clock gating logic allows hardware to seamlessly transition a synchronous set of clocks, for example, all the MPU subsystem clocks.

Figure 6. Main Clock Group Divide and Gating

The clocks derived from main PLL C0-C2 outputs are hardware-managed, meaning hardware ensures that a clean transition occurs, and can have the following control values changed dynamically by software write accesses to the control registers:

  • PLL bypass
  • PLL numerator, denominator, and counters
  • External dividers

For these registers, hardware detects that the write has occurred and performs the correct sequence to ensure that a glitch-free transition to the new clock value occurs. These clocks can pause during the transition.

Table 10.  Main Clock Group Clocks

System Clock Name

Frequency

Constraints and Notes

mpu_clk

Main PLL C0

Clock for MPU subsystem, including CPU0 and CPU1

mpu_l2_ram_clk

mpu_clk/2

Clock for MPU level 2 (L2) RAM

mpu_periph_clk

mpu_clk/4

Clock for MPU snoop control unit (SCU) peripherals, such as the general interrupt controller (GIC)

l3_main_clk

Main PLL C1

Clock for L3 main switch

l3_mp_clk

l3_main_clk/2

Clock for L3 master peripherals (MP) switch

l3_sp_clk

l3_mp_clk or l3_mp_clk/2

Clock for L3 slave peripherals (SP) switch

l4_main_clk

Main PLL C1

Clock for L4 main bus

l4_mp_clk

osc1_clk/16 to 100 MHz divided from main PLL C1 or peripheral PLL C4

Clock for L4 MP bus

l4_sp_clk

osc1_clk/16 to 100 MHz divided from main PLL C1 or peripheral PLL C4

Clock for L4 SP bus

dbg_at_clk

osc1_clk/4 to main PLL C2/2

Clock for CoreSight™ debug trace bus

dbg_trace_clk

osc1_clk/16 to main PLL C2

Clock for CoreSight™ debug Trace Port Interface Unit (TPIU)

dbg_timer_clk

osc1_clk to main PLL C2

Clock for the trace timestamp generator

dbg_clk
8

dbg_at_clk/2 or dbg_at_clk/4

Clock for Debug Access Port (DAP) and debug peripheral bus

main_qspi_clk

Main PLL C3

Quad SPI flash internal logic clock

main_nand_sdmmc_clk

Main PLL C4

Input clock to flash controller clocks block

cfg_clk

osc1_clk to 100_MHz divided from main PLL C5

FPGA manager configuration clock

h2f_user0_clock

osc1_clk to 100_MHz divided from main PLL C5

Auxiliary user clock to the FPGA fabric

7 The maximum frequency depends on the speed grade of the device.
8 dbg_clk must be at least twice as fast as the JTAG clock.