Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

27.4. Configuring the External Memory Interface

The SDRAM tab is one of four tabs on the HPS component. This tab contains the PLL output frequency and phase group.

The HPS supports one memory interface implementing double data rate 2 (DDR2), double data rate 3 (DDR3), and low-power double data rate 2 (LPDDR2) protocols. The interface can be up to 40 bits wide with optional error correction code (ECC).

Configuring the HPS SDRAM controller is similar to configuring any other SDRAM controller in Platform Designer (Standard). There are several important differences:

  • The HPS parameter editor supports all SDRAM protocols with one tab. When you parameterize the SDRAM controller, you must specify the memory protocol: DDR2, DDR3, or LPDDR2.

To select the memory protocol, select DDR2, DDR3, or LPDDR2 from the SDRAM Protocol list in the SDRAM tab. After you select the protocol, settings not applicable to that protocol are disabled.

  • Many HPS SDRAM controller settings are the same as for Intel® dedicated DDR2, DDR3, and LPDDR2 controllers. This section only describes SDRAM parameters that are specific to the HPS component.
  • Because the HPS memory controller is not configurable through the Quartus Prime software, the Controller and Diagnostic tabs are not present in the HPS parameter editor.
  • Some settings, such as the controller settings, are not included because they can only be configured through the register interface, for example by software running on the MPU.
  • Unlike the memory interface clocks in the FPGA, the memory interface clocks for the HPS are initialized by the boot‑up code using values provided by the configuration process. You can accept the values provided by UniPHY, or you can use your own PLL settings, as described in Selecting PLL Output Frequency and Phase.
Note: The HPS does not support external memory interface (EMIF) synthesis generation, compilation, or timing analysis.

The HPS memory controller cannot be bonded with a memory controller on the FPGA portion of the device.

For detailed information about SDRAM controller parameters, refer to the following chapters: