Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024

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5.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync)

The synchronizer using single clock parameterizable macro (ipm_cdc_1clk_sync) synchronizes a one-bit signal with only one clock. You can use the macro for signals that do not have an associated clock. The number of the synchronizer stages is configurable, allowing a range from three to ten stages. You can also specify the initial value on the synchronization register, either 1 or 0 for simulation.

Figure 9. Synchronizer Using Single Clock Parameterizable Macro Block Diagram