Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public

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4.1. I/O PLL Parameterizable Macro Operating Modes

The I/O PLL parameterizable macro supports the following operating modes of the PLL that you specify with the OPERATION_MODE parameter:
  • Direct mode (direct)—the PLL minimizes the feedback path length to produce the smallest possible jitter at the PLL output. In this mode, the PLL does not compensate for any clock networks.
  • Normal mode (normal)—the PLL feedback path source is a global or regional clock network, minimizing clock delay from the input clock pin to the core registers through global or regional clock network.
  • Source Synchronous mode (source_synchronous)—the data and clock signals arrive at the input pins at the same time. In this mode, the signals have the same phase relationship at the clock and data ports of any input output enable register.
  • External Feedback mode (external)—the PLL compensates for the fbclk feedback input to the PLL, thus minimizing the delay between the input clock pin and the feedback clock pin.
  • Non Dedicated Feedback Normal mode (NDFB normal)—enables a non-dedicated feedback path option for the normal compensation mode.
  • Non Dedicated Feedback Source Synchronous mode (NDFB source synchronous)—enables a non-dedicated feedback path option for the source synchronous compensation mode.
  • Zero Delay Buffer mode (zdb)—the PLL feedback path is confined to the dedicated PLL external output pin. The clock port driven off-chip is phase aligned with the clock input for a minimal delay between the clock input and the external clock output.
  • LVDS mode (lvds)—maintains the same data and clock timing relationship at the pins of the internal serializer/deserializer (SERDES) capture register, except that the clock is inverted (180° phase shift). Thus, LVDS mode compensates for the delay of an LVDS clock network.