Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public
Document Table of Contents

4.3. I/O PLL Parameterizable Macro Parameters

Table 10.  I/O PLL Parameterizable Macro Parameters
Parameter Allowed Values Description
REFERENCE_CLOCK_FREQUENCY 10.0 MHz 100.0 MHz Specifies the input frequency for the input clock, refclk, in MHz. The default value is 100.0 MHz. The minimum and maximum values are dependent on the target device.
N_CNT 1-110 Specifies the divide factor of N-counter.
M_CNT 4-160 Specifies the multiply factor of M-counter.
C[0..6]_CNT 1-510 Specifies the divide factor for the output clock (C-counter). The number of C-counter supported is seven.
PLL_SIM_MODEL " " It is a simulation specific parameter to select the technology dependent I/O PLL simulation model. Allowed values are "Stratix 10", "Agilex 7 F-Series", "Agilex 7 (F-Series)", "Agilex 7 I-Series", "Agilex 7 (I-Series)", "Agilex 7 M-Series", "Agilex 7 (M-series), "Agilex 5".
OPERATION_MODE
  • direct
  • normal
  • source_synchronous
  • external
  • NDFB normal
  • NDFB source synchronous
  • zdb
  • lvds
Specifies the operation mode of the PLL. The default operation mode is direct mode.
  • For direct mode, the PLL minimizes the length of the feedback path to produce the smallest possible jitter at the PLL output. The internal-clock and external-clock outputs of the PLL are phase-shifted with respect to the PLL clock input. In this mode, the PLL does not compensate for any clock networks.
  • In normal mode, the PLL compensates for the delay of the internal clock network used by the clock output. If the PLL is also used to drive an external clock output pin, a corresponding phase shift of the signal on the output pin occurs.
  • In source_synchronous mode, the clock delay from pin to I/O input register matches the data delay from pin to I/O input register.
  • For external feedback mode, you must connect the fbclk input port to an input pin. A board-level connection must connect both the input pin and external clock output port, fboutclk. The fbclk port is aligned with the input clock.
  • NDFB normal mode adds a non dedicated feedback path for the normal mode.
  • NDFB source synchronous adds a non dedicated feedback path for the normal mode.
  • In zdb mode, the PLL must feed an external clock output pin and compensate for the delay introduced by that pin. The signal observed on the pin is synchronized to the input clock. The PLL clock output connects to the altbidir port and drives zdbfbclk as an output port. If the PLL also drives the internal clock network, a corresponding phase shift of that network occurs.
  • In lvds mode, the same data and clock timing relationship of the pins at the internal SERDES capture register is maintained. The mode compensates for the delays in LVDS clock network, and between the data pin and clock input pin to the SERDES capture register paths.
CLOCK_TO_COMPENSATE 1 to 7 Index of outclk in the feedback loop for non-dedicated feedback modes ( NDFB normal and NDFB source synchronous).
PHASE_SHIFT[0..6] 0, 90, 180, 270 (degrees) Specifies the phase shift for the corresponding output clock port, outclk [], in picoseconds (ps) or degrees.