Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public

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Document Table of Contents

2.2.3. True Dual-Port RAM VHDL Instantiation Template

True Dual-Port RAM VHDL Instantiation Template

-- Documentation :
-- https://www.intel.com/content/www/us/en/docs/programmable/772350/
-- Macro Location :
-- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd
-- Add the library and use clauses before the design unit declaration
library altera_lnsim; 
use altera_lnsim.altera_lnsim_components.all; 
-- Instantiating TRUE_DUAL_PORT_RAM
 <instance_name> : TRUE_DUAL_PORT_RAM
  generic map (
   -- Port A Parameters
    DATA_WIDTH_A =>                              8,
    ADDR_WIDTH_A =>                              11,
    BYTE_EN_WIDTH_A =>                           1,
    OUT_DATA_REG_CLK_A =>                        "UNREGISTERED",
    OUT_DATA_ACLR_A =>                           "NONE",
    OUT_DATA_SCLR_A =>                           "NONE",
    READ_DURING_WRITE_MODE_A =>                  "NEW_DATA_NO_NBE_READ",
    IN_CLK_EN_A =>                               "NORMAL",
    OUT_CLK_EN_A =>                              "NORMAL",
   -- Port B Parameters
    DATA_WIDTH_B =>                              8,
    ADDR_WIDTH_B =>                              11,
    BYTE_EN_WIDTH_B =>                           1,
    OUT_DATA_REG_CLK_B =>                        "UNREGISTERED",
    OUT_DATA_ACLR_B =>                           "NONE",
    OUT_DATA_SCLR_B =>                           "NONE",
    READ_DURING_WRITE_MODE_B =>                  "NEW_DATA_NO_NBE_READ",
    IN_CLK_EN_B =>                               "NORMAL",
    OUT_CLK_EN_B =>                              "NORMAL",
   -- Parameters common for Port A and Port B
    BYTE_SIZE =>                                 8,
    INIT_FILE =>                                 "",
    INIT_FILE_LAYOUT =>                          "PORT_A",
    MAX_DEPTH =>                                 2048
       )
port map ( 
 clock0 =>    _connected_to_clock0_,    -- input, width = 1   
 clock1 =>    _connected_to_clock1_,    -- input, width = 1   
 clocken0 =>  _connected_to_clocken0_,  -- input, width = 1   
 clocken1 =>  _connected_to_clocken1_,  -- input, width = 1     
 aclr =>      _connected_to_aclr_,      -- input, width = 1     
 sclr =>      _connected_to_sclr_,      -- input, width = 1   
 data_a =>    _connected_to_data_a_,    -- input, width = DATA_WIDTH_A  
 address_a => _connected_to_address_a_, -- input, width = ADDR_WIDTH_A  
 wren_a =>    _connected_to_wren_a_,    -- input, width = 1
 rden_a =>    _connected_to_rden_a_,    -- input, width = 1
 byteena_a => _connected_to_byteena_a_, -- input, width = BYTE_EN_WIDTH_A
 data_b =>    _connected_to_data_b_,    -- input, width = DATA_WIDTH_B
 address_b => _connected_to_address_b_, -- input, width = ADDR_WIDTH_B
 wren_b =>    _connected_to_wren_b_,    -- input, width = 1
 rden_b =>    _connected_to_rden_b_,    -- input, width = 1
 byteena_b => _connected_to_byteena_b_, -- input, width = BYTE_EN_WIDTH_B
 q_a =>       _connected_to_q_a_,       -- output, width = DATA_WIDTH_A  
 q_b =>       _connected_to_q_b_        -- output, width = DATA_WIDTH_B
);