Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public

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5.3.3. Synchronizer Using Single Clock VHDL Instantiation Template

Synchronizer Using Single Clock VHDL Instantiation Template

-- Documentation :
-- https://www.intel.com/content/www/us/en/docs/programmable/772350/
-- Macro Location :
-- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd
-- Add the library and use clauses before the design unit declaration
library altera_lnsim; 
use altera_lnsim.altera_lnsim_components.all; 
-- Instantiating IPM_CDC_1CLK_SYNC
   <instance_name> : IPM_CDC_1CLK_SYNC
      generic map (
         INITIAL_VALUE =>      0,
         NUM_STAGES =>         3
			)
	port map ( 
       clk =>        _connected_to_clk_,        -- input, width = 1  
	   async_in =>   _connected_to_async_in_,   -- input, width = 1  
	   sync_out =>   _connected_to_sync_out_    -- output, width = 1  
			);