Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024

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5.7.1. Pulse Synchronizer Parameterizable Macro Ports

Table 23.  Pulse Synchronizer Parameterizable Macro Ports
Port type Width Description
src_clk Input 1 Synchronizer source clock.
src_rst Input 1 Source reset signal.
src_pulse Input 1 Rising edge of this signal initiates a pulse transfer to the destination clock domain.
dst_clk Input 1 Destination input clock.
dst_rst Input 1 Destination reset signal.
dst_pulse Output 1 Output pulse.