Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public

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5.7.4. Pulse Synchronizer Verilog Instantiation Template

//Quartus Prime Parameterizable Macro Template
	//IPM_CDC_PULSE_SYNC
	//Documentation :
	//https://www.intel.com/content/www/us/en/docs/programmable/772350/
	//Macro Location :
	//$QUARTUS_ROOTDIR/libraries/megafunctions/ipm_cdc_pulse_sync.sv

	ipm_cdc_pulse_sync #(
				.NUM_STAGES                     (3)
	) <instance_name> (
		.src_clk    (_connected_to_src_clk_),	//input, width = 1
		.src_rst	(_connected_to_src_rst_),	//input, width = 1
		.src_pulse  (_connected_to_src_pulse_),  //input, width = 1
		.dst_clk	(_connected_to_dst_clk_),	//input, width = 1
		.dst_rst	(_connected_to_dst_rst_),	//input, width = 1
		.dst_pulse  (_connected_to_dst_pulse_)   //output, width = 1
	);