Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024

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5.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync)

The synchronizer using two clocks parameterizable macro (ipm_cdc_2clks_sync) synchronizes a one-bit signal from the source clock domain to the destination clock domain. The number of the synchronizer stages is configurable, allowing a range from three to ten stages. You can also specify the initial value on the synchronization register, either 1 or 0 for simulation.

Figure 10. Synchronizer Using Two Clocks Parameterizable Macro Block Diagram