Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public

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5.4.1. Synchronizer Using Two Clocks Parameterizable Macro Port Descriptions

Table 17.  Synchronizer Using Two Clocks Parameterizable Macro Port Descriptions
Port Type Width Required Description
src_clk Input 1 Yes Clock signal for source clock domain.
src_sig Input 1 Yes Input signal to be synchronized to destination clock domain.
dst_clk Input 1 Yes Clock signal for the destination clock domain.
dst_sig Output 1 Yes Output signal synchronized to the destination clock domain.