Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Document Table of Contents

4.2. I/O PLL Parameterizable Macro Port Descriptions

Table 9.  I/O PLL Parameterizable Macro Port Descriptions
Port Type Required Description
reflck Input Required The reference clock source that drives the I/O PLL.
locked Output Optional Signals that the I/O PLL is locked to the refclk. This port is driven high when the PLL acquires lock. The port remains high as long as the I/O PLL is locked. The I/O PLL asserts the locked port when the phases and frequencies of the reference clock and feedback clock are the same or within the lock circuit tolerance. When the difference between the two clock signals exceeds the lock circuit tolerance, the I/O PLL loses lock.
reset Input Required Triggers the I/O PLL reset. This is the asynchronous reset port for the output clocks. Drive this port high to reset all output clocks to the value of 0.
outclk[0..6] Output Optional Output clock from the I/O PLL.
fbclk input Optional

The external feedback input port for the I/O PLL. This port is required if the I/O PLL must operate in external feedback mode or zero-delay buffer mode. To complete the feedback loop, a board-level connection must connect the fbclk port and the external clock output port of the I/O PLL.

fbclkout output Optional

The port that feeds the fbclk port through the mimic circuitry.

extclk_out output Optional

Output clock directly connecting to the output buffer.

zdbfbclk Bidirectional Optional

The bidirectional port that connects to the mimic circuitry. This port must connect to a bidirectional pin that is placed on the positive feedback dedicated output pin of the I/O PLL.