Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public

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5.1.1. Synchronous Reset Synchronizer Parameterizable Macro Port Descriptions

Table 11.  Synchronous Reset Synchronizer Parameterizable Macro Port Descriptions
Port Type Width Required Description
clk Input 1 Yes Synchronizer reset clock port.
srst_in Input 1 Yes Synchronous reset input port.
srst_out Output 1 Yes Synchronous reset output port.