Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public

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4.4. I/O PLL VHDL Instantiation Template

I/O PLL VHDL Instantiation Template

-- Documentation :
-- https://www.intel.com/content/www/us/en/docs/programmable/772350/
-- Macro Location :
-- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd
-- Add the library and use clauses before the design unit declaration
library altera_lnsim; 
use altera_lnsim.altera_lnsim_components.all; 

-- Configuration in the template is set to default values to generate PLL clocks,
 kindly refer IPM IOPLL UserGuide for more use cases.

-- Instantiating IPM_IOPLL
 <instance_name> : IPM_IOPLL
  generic map (
  REFERENCE_CLOCK_FREQUENCY => "100.0 MHz",
  N_CNT =>                      1,
  M_CNT =>                      6,
  C0_CNT =>                     1,           	
  C1_CNT =>                     1,           	
  C2_CNT =>                     1,           	
  C3_CNT =>                     1,           	
  C4_CNT =>                     1,           	
  C5_CNT =>                     1,           	
  C6_CNT =>                     1,
  OPERATION_MODE =>             "direct",
  CLOCK_TO_COMPENSATE =>        1,
  PHASE_SHIFT0 =>               0,
  PHASE_SHIFT1 =>               0,
  PHASE_SHIFT2 =>               0,
  PHASE_SHIFT3 =>               0,
  PHASE_SHIFT4 =>               0,
  PHASE_SHIFT5 =>               0,
  PHASE_SHIFT6 =>               0,
  PLL_SIM_MODEL =>              ""   
                               // It is a simulation specific parameter 
                               // to select the technology dependent IOPLL 
                               // simulation model. Allowed values are 
                               // "Stratix 10", "Agilex 7 F-Series", 
                               // "Agilex 7 (F-Series)", "Agilex 7 I-Series",
                               // "Agilex 7 (I-Series)", "Agilex 7 M-Series", 
                               // "Agilex 7 (M-Series)", "Agilex 5"	
			)
port map (
  refclk =>       _connected_to_refclk_,     -- input,  width = 1
  reset =>        _connected_to_reset_,      -- input,  width = 1 
  outclk0 =>      _connected_to_outclk0_,    -- output, width = 1
  outclk1 =>      _connected_to_outclk1_,    -- output, width = 1
  outclk2 =>      _connected_to_outclk2_,    -- output, width = 1
  outclk3 =>      _connected_to_outclk3_,    -- output, width = 1
  outclk4 =>      _connected_to_outclk4_,    -- output, width = 1
  outclk5 =>      _connected_to_outclk5_,    -- output, width = 1
  outclk6 =>      _connected_to_outclk6_,    -- output, width = 1
  locked =>       _connected_to_locked_,     -- output, width = 1
  fbclk =>        _connected_to_fbclk_,      -- input,  width = 1
  fbclkout =>     _connected_to_fbclkout_,   -- output, width = 1
  extclk_out =>   _connected_to_extclk_out_, -- output, width = 1
  zdbfbclk =>     _connected_to_zdbfbclk_    -- inout,  width = 1
   );