Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public

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5.7.3. Pulse Synchronizer VHDL Instantiation Template

Pulse Synchronizer VHDL Instantiation Template

-- Documentation :
-- https://www.intel.com/content/www/us/en/docs/programmable/772350/
-- Macro Location :
-- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd
-- Add the library and use clauses before the design unit declaration
library altera_lnsim; 
use altera_lnsim.altera_lnsim_components.all; 
-- Instantiating IPM_CDC_PULSE_SYNC
	<instance_name> : IPM_CDC_PULSE_SYNC
	generic map (
			NUM_STAGES =>			3
		    )
	port map ( 
			src_clk =>     _connected_to_src_clk_,    -- input, width = 1	  
			src_rst =>     _connected_to_src_rst_,    -- input, width = 1
			src_pulse =>   _connected_to_src_pulse_,  -- input, width = 1
		    dst_clk =>     _connected_to_dst_clk_,    -- input, width = 1
			dst_rst =>     _connected_to_dst_rst_,    -- input, width = 1
			dst_pulse =>   _connected_to_dst_pulse_   --output, width = 1
			);