Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024

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5. CDC Parameterizable Macros

The CDC parameterizable macros allow you to generate various clock domain crossing (CDC) blocks. The current version of the Quartus® Prime Pro Edition software supports the following synchronizer parameterizable macros:

  • Synchronous reset synchronizer parameterizable macro (ipm_cdc_sync_rst)
  • Asynchronous reset synchronizer parameterizable macro (ipm_cdc_async_rst)
  • Single bit synchronizer using single clock parameterizable macro (ipm_cdc_1clk_sync)
  • Single bit synchronizer using two clocks parameterizable macro (ipm_cdc_2clks_sync)
  • Glitchless Clock MUX parameterizable macro (ipm_cdc_glitchless_clk_mux)
  • Bus synchronizer parameterizable macro (ipm_cdc_bus_sync)

This section provides the block diagrams, port descriptions, parameter tables, and instantiation templates for these parameterizable macros.