Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024

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3. FIFO Parameterizable Macros

The FIFO is First-in First-out, meaning that words written first in the FIFO are read back first. The FIFO acts as a temporary memory where you can write data and read it back later. You can apply the FIFO functions in data buffering applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock domains. SYNC_FIFO/sync_fifo is a synchronous FIFO that uses the same clock signal to perform the read and write operations. ASYNC_FIFO/async_fifo is an asynchronous FIFO that uses the rdclk or wrclk signal to perform the read or write operation, respectively.

You can instantiate the parameterizable SYNC_FIFO/sync_fifo and ASYNC_FIFO/async_fifo modules using the instantiation templates available in Quartus® Prime Pro Edition software, starting from version 23.1. You can instantiate the SYNC_FIFO/sync_fifo module using the synchronous FIFO template (sync_fifo or SYNC_FIFO). You can instantiate the ASYNC_FIFO/async_fifo module using the asynchronous FIFO template (async_fifo or ASYNC_FIFO).

This section provides the block diagrams, port descriptions, parameter tables, and instantiation templates of the SYNC_FIFO/sync_fifo and ASYNC_FIFO/async_fifo macro modules. For more information on these FIFO modules, such as the timing requirements, metastability protection, and operating modes, refer to the FIFO Intel FPGA IP User Guide.