Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024

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5.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst)

The asynchronous reset synchronizer parameterizable macro (ipm_cdc_async_rst) synchronizes an asynchronous reset signal to the destination clock domain. The generated output asserts asynchronously and de-asserts synchronously to the destination clock domain. The number of synchronizer stages is configurable, allowing a range from three to ten stages. The default reset type is ACTIVE_HIGH, but you can specify the ACTIVE_HIGH or ACTIVE_LOW type of the reset signal with the RST_TYPE parameter.

Figure 8. Asynchronous Reset Synchronizer Parameterizable Macro Block Diagram