Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public

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5.1.4. Synchronous Reset Synchronizer Verilog Instantiation Template

Synchronous Reset Synchronizer Verilog Instantiation Template

//Quartus Prime Parameterizable Macro Template
//IPM_CDC_SYNC_RST
//Documentation :
//https://www.intel.com/content/www/us/en/docs/programmable/772350/
//Macro Location :
//$QUARTUS_ROOTDIR/libraries/megafunctions/ipm_cdc_sync_rst.sv
	
   ipm_cdc_sync_rst #(
      .RST_TYPE           ("ACTIVE_HIGH"),
      .NUM_STAGES         (3)
	) <instance_name> (
      .clk         (_connected_to_clk_),      //input, width = 1
      .srst_in     (_connected_to_srst_in_),  //input, width = 1
      .srst_out    (_connected_to_srst_out_)  //output, width = 1
	);