Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public

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5.5.3. Glitchless Clock MUX VHDL Instantiation Template

Glitchless Clock MUX VHDL Instantiation Template

-- Documentation :
-- https://www.intel.com/content/www/us/en/docs/programmable/772350/
-- Macro Location :
-- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd
-- Add the library and use clauses before the design unit declaration
library altera_lnsim; 
use altera_lnsim.altera_lnsim_components.all; 
-- Instantiating IPM_CDC_GLITCHLESS_CLK_MUX
	<instance_name> : IPM_CDC_GLITCHLESS_CLK_MUX
	generic map (
			CLK_TYPE =>         "RELATED_CLKS"
			)
	port map ( 
		sel =>      _connected_to_sel_,     -- input, width = 1	  
		clk_A =>    _connected_to_clk_A_,   -- input, width = 1
		clk_B =>  _connected_to_clk_B_,	 -- input, width = 1
		clk_out =>  _connected_to_clk_out_  -- output, width = 1	
		);