Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 4/10/2024
Public

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5.5.4. Glitchless Clock MUX Verilog Instantiation Template

Glitchless Clock MUX Verilog Instantiation Template

//Quartus Prime Parameterizable Macro Template
//IPM_CDC_GLITCHLESS_CLK_MUX
//Documentation :
//https://www.intel.com/content/www/us/en/docs/programmable/772350/
//Macro Location :
//$QUARTUS_ROOTDIR/libraries/megafunctions/ipm_cdc_glitchless_clk_mux.sv
	
	ipm_cdc_glitchless_clk_mux #(
	CLK_TYPE                   ("RELATED_CLKS")
	) <instance_name> (
     .sel		(_connected_to_sel_),            //input, width = 1
     .clk_A      (_connected_to_clk_A_),          //input, width = 1
     .clk_B      (_connected_to_clk_B_),          //input, width = 1
     .clk_out    (_connected_to_clk_out_)         //output, width = 1
	);