Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 9/30/2024
Public

Visible to Intel only — GUID: eab1692918509370

Ixiasoft

Document Table of Contents

5.3.1. Synchronizer Using Single Clock Parameterizable Macro Port Descriptions

Table 15.  Synchronizer Using Single Clock Parameterizable Macro Port Descriptions
Port Type Width Required Description
clk Input 1 Yes Synchronizer clock.
async_in Input 1 Yes Input signal asynchronous to clk.
sync_out Output 1 Yes Output signal synchronized to output clock domain.