Parameterizable Macros for Intel® FPGAs User Guide

Download PDF
ID 772350
Date 11/05/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Parameterizable Macros for Intel FPGAs Overview 2. Dual-Port Random Access Memory (RAM) Parameterizable Macros 3. FIFO Parameterizable Macros 4. I/O PLL Parameterizable Macro (ipm_iopll) 5. CDC Parameterizable Macros 6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide 7. Parameterizable Macros for Intel FPGAs User Guide Archives
1. Parameterizable Macros for Intel FPGAs Overview x
1.1. Available Parameterizable Macros for Intel FPGAs 1.2. Inserting HDL Code from Parameterizable Macro Templates
2. Dual-Port Random Access Memory (RAM) Parameterizable Macros x
2.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) 2.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram)
2.1. Simple Dual-Port RAM Parameterizable Macro (simple_dual_port_ram) x
2.1.1. Simple Dual-Port RAM Parameterizable Macro Port Descriptions 2.1.2. Simple Dual-Port RAM Parameterizable Macro Parameters 2.1.3. Simple Dual-Port RAM VHDL Instantiation Template 2.1.4. Simple Dual-Port RAM Verilog Instantiation Template 2.1.5. Simple Dual-Port RAM SystemVerilog Instantiation Template
2.2. True Dual-Port RAM Parameterizable Macro (true_dual_port_ram) x
2.2.1. True Dual-Port RAM Parameterizable Macro Port Descriptions 2.2.2. True Dual-Port RAM Parameterizable Macro Parameters 2.2.3. True Dual-Port RAM VHDL Instantiation Template 2.2.4. True Dual-Port RAM Verilog Instantiation Template 2.2.5. True Dual-Port RAM SystemVerilog Instantiation Template
3. FIFO Parameterizable Macros x
3.1. Synchronous FIFO Parameterizable Macro (sync_fifo) 3.2. Asynchronous FIFO Parameterizable Macro (async_fifo)
3.1. Synchronous FIFO Parameterizable Macro (sync_fifo) x
3.1.1. Synchronous FIFO Parameterizable Macro Port Descriptions 3.1.2. Synchronous FIFO Parameterizable Macro Parameters 3.1.3. Synchronous FIFO VHDL Instantiation Template 3.1.4. Synchronous FIFO Verilog Instantiation Template 3.1.5. Synchronous FIFO SystemVerilog Instantiation Template
3.2. Asynchronous FIFO Parameterizable Macro (async_fifo) x
3.2.1. Asynchronous FIFO Parameterizable Macro Port Descriptions 3.2.2. Asynchronous FIFO Parameterizable Macro Parameters 3.2.3. Asynchronous FIFO VHDL Instantiation Template 3.2.4. Asynchronous FIFO Verilog Instantiation Template 3.2.5. Asynchronous FIFO SystemVerilog Instantiation Template
4. I/O PLL Parameterizable Macro (ipm_iopll) x
4.1. I/O PLL Parameterizable Macro Operating Modes 4.2. I/O PLL Parameterizable Macro Port Descriptions 4.3. I/O PLL Parameterizable Macro Parameters 4.4. I/O PLL VHDL Instantiation Template 4.5. I/O PLL Verilog Instantiation Template 4.6. I/O PLL SystemVerilog Instantiation Template
5. CDC Parameterizable Macros x
5.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) 5.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) 5.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) 5.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) 5.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) 5.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync) 5.7. Pulse Synchronizer Parameterizable Macro (ipm_cdc_pulse_sync)
5.1. Synchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_sync_rst) x
5.1.1. Synchronous Reset Synchronizer Parameterizable Macro Port Descriptions 5.1.2. Synchronous Reset Synchronizer Parameterizable Macro Parameters 5.1.3. Synchronous Reset Synchronizer VHDL Instantiation Template 5.1.4. Synchronous Reset Synchronizer Verilog Instantiation Template 5.1.5. Synchronous Reset Synchronizer SystemVerilog Instantiation Template
5.2. Asynchronous Reset Synchronizer Parameterizable Macro (ipm_cdc_async_rst) x
5.2.1. Asynchronous Reset Synchronizer Parameterizable Macro Port Descriptions 5.2.2. Asynchronous Reset Synchronizer Parameterizable Macro Parameters 5.2.3. Asynchronous Reset Synchronizer VHDL Instantiation Template 5.2.4. Asynchronous Reset Synchronizer Verilog Instantiation Template 5.2.5. Asynchronous Reset Synchronizer SystemVerilog Instantiation Template
5.3. Synchronizer Using Single Clock Parameterizable Macro (ipm_cdc_1clk_sync) x
5.3.1. Synchronizer Using Single Clock Parameterizable Macro Port Descriptions 5.3.2. Synchronizer Using Single Clock Parameterizable Macro Parameters 5.3.3. Synchronizer Using Single Clock VHDL Instantiation Template 5.3.4. Synchronizer Using Single Clock Verilog Instantiation Template 5.3.5. Synchronizer Using Single Clock SystemVerilog Instantiation Template
5.4. Synchronizer Using Two Clocks Parameterizable Macro (ipm_cdc_2clks_sync) x
5.4.1. Synchronizer Using Two Clocks Parameterizable Macro Port Descriptions 5.4.2. Synchronizer Using Two Clocks Parameterizable Macro Parameters 5.4.3. Synchronizer Using Two Clocks VHDL Instantiation Template 5.4.4. Synchronizer Using Two Clocks Verilog Instantiation Template 5.4.5. Synchronizer Using Two Clocks SystemVerilog Instantiation Template
5.5. Glitchless Clock MUX Parameterizable Macro (ipm_cdc_glitchless_clk_mux) x
5.5.1. Glitchless Clock MUX Parameterizable Macro Port Descriptions 5.5.2. Glitchless Clock MUX Parameterizable Macro Parameters 5.5.3. Glitchless Clock MUX VHDL Instantiation Template 5.5.4. Glitchless Clock MUX Verilog Instantiation Template 5.5.5. Glitchless Clock MUX SystemVerilog Instantiation Template
5.6. Bus Synchronizer Parameterizable Macro (ipm_cdc_bus_sync) x
5.6.1. Bus Synchronizer Parameterizable Macro Port Descriptions 5.6.2. Bus Synchronizer Parameterizable Macro Parameters 5.6.3. Bus Synchronizer VHDL Instantiation Template 5.6.4. Bus Synchronizer Verilog Instantiation Template 5.6.5. Bus Synchronizer SystemVerilog Instantiation Template
5.7. Pulse Synchronizer Parameterizable Macro (ipm_cdc_pulse_sync) x
5.7.1. Pulse Synchronizer Parameterizable Macro Ports 5.7.2. Pulse Synchronizer Parameterizable Macro Parameters 5.7.3. Pulse Synchronizer VHDL Instantiation Template 5.7.4. Pulse Synchronizer Verilog Instantiation Template 5.7.5. Pulse Synchronizer SystemVerilog Instantiation Template
Answers to Top FAQs
1. Parameterizable Macros for Intel FPGAs Overview
2. Dual-Port Random Access Memory (RAM) Parameterizable Macros
3. FIFO Parameterizable Macros
4. I/O PLL Parameterizable Macro (ipm_iopll)
5. CDC Parameterizable Macros
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
7. Parameterizable Macros for Intel FPGAs User Guide Archives

3.2.2. Asynchronous FIFO Parameterizable Macro Parameters

Table 8.  ASYNC_FIFO Parameterizable Macro Parameters
Parameter Allowed Values Description
DATA_WIDTH_A Device and ADDR_WIDTH_A dependent Specifies the width of the data and q ports. For ASYNC_FIFO, this parameter specifies only the width of the data port. The default value is 8.
DATA_WIDTH_B Device and ADDR_WIDTH_B dependent Specifies the width of the q port for ASYNC_FIFO mixed width FIFO macro (If similar port data is used, give value as DATA_WIDTH_B = DATA_WIDTH_A). The default value is 8.
ADDR_WIDTH_A Device and DATA_WIDTH_A dependent Specifies the width of the rdusedw and wrusedw ports for ASYNC_FIFO. For ASYNC_FIFO mixed width, it only represents the width of the wrusedw port. The default value is 11.
ADDR_WIDTH_B Device and DATA_WIDTH_B dependent Specifies the width of the rdusedw ports for ASYNC_FIFO mixed width FIFO (If similar port data is used, give value as ADDR_WIDTH_B = ADDR_WIDTH_A). The default value is 11.
ENABLE_SHOWAHEAD

ON

OFF

Specifies whether the FIFO is in normal mode (OFF) or show-ahead mode (ON).

For normal mode, the FIFO treats the rdreq port as a normal read request that only performs read operation when the port is asserted.

For show-ahead mode, FIFO treats the rdreq port as a read-acknowledge that automatically outputs the first word of valid data in the FIFO (when the empty port is low) without asserting the rdreq signal. Asserting the rdreq signal causes the FIFO to output the next data word, if available.

Setting ON to this parameter may reduce performance.
OVERFLOW CHECKING

ON

OFF

 Specifies whether or not to enable the protection circuitry for overflow checking that disables the wrreq port when the FIFO is full. The values are ON or OFF. If omitted, the default is ON.
UNDERFLOW_CHECKING

ON

OFF

 Specifies whether or not to enable the protection circuitry for underflow checking that disables the rdreq port when the FIFO is empty. The values are ON or OFF. If omitted, the default is ON.
ADD_USEDW_MSB_BIT

ON

OFF

 Increases the width of the rdusedw and wrusedw ports by one bit. By increasing the width, it prevents the FIFO from rolling over to zero when it is full. The values are ON or OFF. The default value is OFF.

RDSYNC_DELAYPIPE

WRSYNC_DELAYPIPE

 2 (default) Specify the number of synchronization stages in the cross clock domain. The value of the RDSYNC_DELAYPIPE parameter relates the synchronization stages from the write control logic to the read control logic; the WRSYNC_DELAYPIPE parameter relates the synchronization stages from the read control logic to the write control logic.
MAXIMUM_DEPTH AUTO, 32, 64, 128, 256, 512, 1024, 2048 (default), 4096, 8192, 16384 Specifies the available slicing depth of the RAM slices.
WRITE_ACLR_SYNC

ON

OFF

 Specifies whether or not to add a circuit that causes the aclr port to be internally synchronized by the wrclk clock. Adding the circuit prevents the race condition between the wrreq and aclr ports that could corrupt the FIFO. The values are ON or OFF. The default value is OFF.
READ_ACLR_SYNC

ON

OFF

 Specifies whether or not to add a circuit that causes the aclr port to be internally synchronized by the rdclk clock. Adding the circuit prevents the race condition between the rdreq and aclr ports that could corrupt the FIFO. The values are ON or OFF. The default value is OFF.
ADD_RAM_OUTPUT_REGISTER

ON

OFF

 Specifies whether to register the q output. The values are ON and OFF. The default value is OFF.
BYTE_SIZE

5

8 (default)

9

10

 Specifies the size of the byte for byte-enable mode
BYTE_EN_WIDTH 1 (default)

Width of the byte-enable bus at Port A.

This width should be equal to DATA_WIDTH_A divided by BYTE_SIZE.
Note: The Quartus® Prime Pro Edition software version 23.2 includes the following parameter changes with respect to prior parameterizable macros versions. If you are using a software version earlier than 23.2, you must update your RTL code accordingly:
  1. The parameter RAM_BLOCK_TYPE (AUTO, MLAB, M20K) is removed in Quartus® Prime Pro Edition software version 23.2 and later.
  2. The parameter MAXIMUM_DEPTH allowed values are only AUTO, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, and 16384 in Quartus® Prime Pro Edition software version 23.2 and later.
Level Two Title