Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 10/29/2021

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Document Table of Contents

4.4.6. User MSI-X Interface

User logic requests DMA engine to send an event interrupt for a queue associated with a PF/VF.

Table 29.  User MSI-X Interface

Interface Clock Domain for H-Tile: coreclkout_hip

Interface Clock Domain for P-Tile and F-Tile: app_clk

Signal Name I/O Description


The valid signal qualifies valid data on any cycle with data transfer.



On interfaces supporting backpressure, the sink asserts ready to mark the cycles where transfers may take place.

usr_event_msix_data_i [15:0] Input


Note: msix_queue_dir Queue direction. D2H = 0, H2D =1