Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 10/29/2021
Public

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4.4.1. Avalon-MM PIO Master

The Avalon-MM PIO Master interface is used to write to /read from external registers implemented in the user logic.

Table 24.  Avalon-MM PIO Master

Interface Clock Domain for H-Tile: coreclkout_hip

Interface Clock Domain for P-Tile and F-Tile: app_clk

Signal Name I/O Type Description
rx_pio_address_o[n:0] Output

PIO Read/Write Address.

H-Tile:
<n> = (14+PIO BAR2 Address Width)-1
P-Tile and F-Tile:
<n> = (15+PIO BAR2 Address Width)-1
Address = {vf_active, clog2(PF_NUM), clog2(VF_NUM), PIO BAR2 Address}
rx_pio_writedata_o[63:0] Output PIO Write Data Payload.
rx_pio_byteenable_o[7:0] Output PIO Write Data Byte Enable.
rx_pio_write_o Output PIO Write.
rx_pio_read_o Output PIO Read
rx_pio_burstcount_o[3:0] Output PIO Write Burst Count.
rx_pio_waitrequest_i Input PIO Write WaitRequest.
rx_pio_writeresponsevalid_i Input PIO response valid to a write request
rx_pio_readdata_i[63:0] Input PIO Read Data.
rx_pio_readdatavalid_i Input PIO Read data valid
rx_pio_response_i[1:0] Input PIO response. Reserved for future release. Tie to 0.

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