Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 10/29/2021

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4.2. Clocks

Table 22.  Multi Channel DMA IP for PCI Express Clock Signals
Signal Name I/O Type Description Clock Frequency
refclk Input

PCIe reference clock defined by the PCIe specification.

This input reference clock must be stable and free-running at device power-up for a successful device configuration.

100 MHz ± 300 ppm

coreclkout_hip Output

This is an output clock provided to user logic. Avalon-MM / Avalon-ST user interfaces are synchronous to this clock.

250 MHz
P-Tile and F-Tile
refclk0 Input PCIe reference clock defined by the PCIe specification. These clocks must be free-running and driven by the single clock source.

100 MHz ± 300 ppm

refclk1 Input
coreclkout_hip Output


Note: Not available for P-Tile. In earlier versions, this signal was present. Manual upgrade is required.
app_clk Output Application clock

Gen3: 250 MHz

Gen4: 400 MHz (Intel Stratix 10 DX), 500 MHz (Intel Agilex)

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