Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 10/29/2021

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Document Table of Contents PCIe0 Link

Table 57.  PCIe0 Link



Default Value


Link port number (Root Port only)



Sets the read-only value of the port number field in the Link Capabilities register. This parameter is for Root Ports only. It should not be changed.

Slot clock configuration

On/Off On

When you turn this option On, indicates that the Endpoint uses the same physical reference clock that the system provides on the connector.

When Off, the IP core uses an independent clock regardless of the presence of a reference clock on the connector. This parameter sets the Slot Clock Configuration bit (bit 12) in the PCI Express Link Status register.

You cannot enable this option when the Enable SRIS Mode option is enabled.

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