Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 10/29/2021

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Document Table of Contents

4.8. Hard IP Reconfiguration Interface

Table 34.  Hard IP Reconfiguration Interface
Signal Name I/O Description
usr_hip_reconfig_clk Input

Reconfiguration clock. 50 MHz - 125 MHz

(Range) 100 MHz (Recommended)

usr_hip_reconfig_readdata_o[7:0] Output read data out
usr_hip_reconfig_readdatavalid_o Output

When asserted, the data on hip_reconfig_readdata[7:0] is


usr_hip_reconfig_write_i Input Write enable
usr_hip_reconfig_read_i Input Read enable
usr_hip_reconfig_address_i[20:0] Input Reconfig register address
usr_hip_reconfig_writedata_i[7:0] Input Write data
usr_hip_reconfig_waitrequest_o Output When asserted, this signal indicates that the IP core is not ready to respond to a request.