Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 10/29/2021

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Document Table of Contents

2.1.1. Endpoint Mode

  • PCIe Gen4/Gen3 x16/x8 in Intel® Stratix® 10 DX and Intel® Agilex™ devices.
    Note: MCDMA P-Tile IP does not support x8x8 port bifurcation.
  • MCDMA P-Tile: PCIe Gen3 x16/x8 in Intel® Stratix® 10 GX and Intel® Stratix® 10 MX devices.
    Note: MCDMA P-Tile IP doesn't support Root Port in x8 link width.
  • MCDMA F-Tile: PCIe Gen4/Gen3 x16/x8 in Intel Agilex device
  • User Mode options:
    • Multi Channel DMA
    • Bursting Avalon Master (BAM)
    • Bursting Avalon Slave (BAS)
    • BAM and BAS
    • BAM and MCDMA
  • Supports up to 2K DMA channels.
    • Table 2.  Maximum DMA channels
      Device MCDMA Interface Type
      AVMM 4 AVST Ports 1 AVST Port

      Intel® Stratix® 10 GX

      Intel® Stratix® 10 MX

      Intel® Stratix® 10 DX

      Intel® Agilex™

      2048* 4 2048*
      Note: * = Maximum 512 channels per Function
  • Per Descriptor completion notification with MSI-X or Writebacks
  • Architectural support for 'Head-of-line' blocking prevention for 4 Avalon-ST ports
  • Option to select Avalon-MM or Avalon-ST DMA for user logic interface
  • Alternate option to enable 4 Avalon-ST DMA ports with 1 DMA channel per port
  • SR-IOV
    Note: SRIOV is only enabled when a single port configuration (AVMM and AVST 1 Port) is enabled in the Multi Channel DMA IP
  • User MSI-X
    Note: MSI is currently not supported
  • FLR
    Note: User MSI-X and FLR are supported only when Multi Channel DMA mode is enabled.