Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 10/29/2021
Public

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5.1.5. Configuration, Debug and Extension Options

Table 43.  PCIe0 Configuration, Debug and Extension Options
Parameter Value Description
Enable HIP dynamic reconfiguration of PCIe read-only registers On / Off

When on, creates an Avalon-MM slave interface that software can drive to update global configuration registers which are read-only at run time.

Enable transceiver dynamic reconfiguration On / Off

When on, creates an Avalon-MM slave interface that software can drive to update Transceiver reconfiguration registers

Enable Native PHY, LCPLL, and fPLL ADME for Toolkit On / Off

When on, Native PHY and ATXPLL and fPLL ADME are enabled for Transceiver Toolkit. Must enable transceiver dynamic reconfiguration before enabling ADME

Enable PCIe Link Inspector On / Off

When on, PCIe link inspector is enabled. Must enable HIP dynamic reconfiguration, transceiver dynamic reconfiguration and ADME for Toolkit to use PCIe link inspector

Enable PCIe Link Inspector AVMM Interface On / Off

When on, PCIe link inspector AVMM interface is exported. When on, JTAG to Avalon Bridge IP instantiation is included in the Example Design generation for debug

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