Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 10/29/2021
Public

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Document Table of Contents

8.2.2.3. User MSI-X

Each DMA queue is allocated with 2 interrupts:
  • For reporting Descriptor completion status.
  • For User MSI-X: If some event or error happens, user logic generates the User MSI-X.

Application is responsible to poll for a set of registered interrupt addresses and if User MSI-X is triggered, the corresponding registered interrupt callback gets called. Currently, this callback address is being sent in private pointers of queue config registers.

For D2H queue

int
rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id,
                                               uint16_t nb_rx_desc, unsigned int socket_id,
                                               const struct rte_eth_rxconf *rx_conf,
                                               struct rte_mempool *mp)
struct rte_eth_rxconf {
        struct rte_eth_thresh rx_thresh; /**< RX ring threshold registers. */
        uint16_t rx_free_thresh; /**< Drives the freeing of RX descriptors. */
       uint64_t offloads;
	…
        uint64_t reserved_64s[2]; /**< Reserved for future fields */
        void *reserved_ptrs[2];    reserved_ptrs[0] should be populated with user MSIX callback
};

For H2D queue

Int
rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
                                               uint16_t nb_tx_desc, unsigned int socket_id,
                                               const struct rte_eth_rxconf *tx_conf)
struct rte_eth_txconf {
        struct rte_eth_thresh tx_thresh; /**< TX ring threshold registers. */
        uint16_t tx_rs_thresh; /**< Drives the setting of RS bit on TXDs. */
        uint16_t tx_free_thresh; 
	…
        uint64_t reserved_64s[2]; /**< Reserved for future fields */
        void *reserved_ptrs[2];      reserved_ptrs[0] should be populated with user MSIX callback
};

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