Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 10/29/2021
Public

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4.12. User Event MSI-X Request Interface

User logic can request DMA engine to send an event interrupt for a queue associated with a PF/VF.

Table 37.  User FLR Interface Signals
Signal Name I/O Description
usr_event_msix_valid _i Input

The valid signal qualifies valid data on any cycle with data transfer.

usr_event_msix_ready_o Output

On interfaces supporting backpressure, the sink asserts ready to mark the cycles where transfers may take place.

usr_event_msix_data_i[15:0] Input

{rsvd[3:0J,msix_queue_dir, msix_queue_num_i[10:0]}

Note: msix_queue_dir Queue Direction. D2H = 0, H2D=1

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