Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 10/29/2021

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3.1.4. Avalon-MM PIO Master

The Avalon-MM PIO Master bypasses the DMA block and provides a way for the Host to do MMIO read/write to CSR registers of user logic. PCIe BAR2 is mapped to the Avalon-MM PIO Master. Any TLP targeting BAR2 is forwarded to the user logic. TLP address targeting the PIO interface should be 8 bytes aligned. The PIO interface supports non-bursting 64-bit write and read transfers.

The Avalon-MM PIO Master is present only if you select Multi Channel DMA User Mode for MCDMA Settings in the IP Parameter Editor GUI. The Avalon-MM PIO Master is always present irrespective of the Interface type (Avalon-ST/Avalon-MM) that you select.

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