Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Signal Tap Intel® FPGA IP Parameters

The Signal Tap Intel® FPGA IP has the following parameters:
Table 8.   Signal Tap Intel® FPGA IP Parameters
Parameter Groups Parameter Descriptions
  • Data Input Port Width—from 1 to 4096. Default is 1.
  • Sample Depth—number of samples to collect from 0-128K. Default is 128.
  • RAM type—memory type for sample collection and storage. The Auto (default), M20K/M10K/M9K, MLAB/LUTRAM, and M144K options are available.
Segmented Acquisition Specifies options for organizing the captured data buffer:
  • Segmented—the memory space is split into separate buffers. Each buffer acts as a separate FIFO with its own set of trigger conditions, and behaves as a non-segmented buffer. Only a single buffer is active during an acquisition. Default is off.
  • Number of Segments—specifies the number of segments in each memory space. Default is 2.
  • Samples per Segments—the number of samples Signal Tap captures per segment. Default is 64.
Storage Qualifier Specifies the Continuous or Input Port method, and whether to Record data discontinuities.
  • Trigger Input Port Width—from 1 to 4096. Default is 1.
  • Trigger Conditions—number of trigger conditions or levels you are implementing 1-10. Default is 1.
  • Trigger In—enables and creates a port for the Trigger In.
  • Trigger Out—enables and creates a port for the Trigger Out.
Pipelining The Pipeline Factor specifies the levels of pipelining added for potential fMAX improvement from 0 to 5. Default is 0.

Did you find the information on this page useful?

Characters remaining:

Feedback Message