Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022
Public

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2.9.3.2. PR Design Setup for Signal Tap Debug

Figure 90. Setting Up PR Design for Debug with Signal Tap

To debug a PR design, you must instantiate SLD JTAG bridges when generating the base revision, and then define debug components for all PR personas. Optionally, you can specify signals to tap in the static region. After configuring all the PR personas in the design, you can continue the PR design flow.

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