2.9.1. Signal Tap and Simulator Integration
You can use Signal Tap signal and acquisition data directly in your supported simulator for enhanced visibility into internal signal states in a design hierarchy. The Add Simulator Aware Nodes command intelligently analyzes the circuit to determine the minimum set of nodes needed to tap to gain full visibility into the selected hierarchy's cone of logic.
Signal Tap can also transform the Signal Tap data into an RTL simulation testbench for any level of the design hierarchy. This simulation testbench allows you to export acquired Signal Tap hardware data directly into your RTL simulator and observe signal states beyond Signal Tap observability.
The following topics describe these Signal Tap and Simulator Integration features in detail:
Simulator Integration Beta Limitations
- Supports only Verilog HDL simulation.
- Supports testbench generation only within the current project directory.
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