Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.16. Design Debugging with the Signal Tap Logic Analyzer Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2022.07.08 22.1
  • Fixed broken link in Custom State-Based Triggering Flow Examples.
2022.03.28 22.1
  • Added Organizing Signals in the Signal Tap Logic Analyzer topic.
  • Removed incorrect links from Intel® Quartus® Prime Pro Edition User Guide Debug Tools Archives topic.
2021.10.13 21.3
  • Added Recompiling Only Signal Tap Changes topic.
  • Changed title of Prevent Changes Requiring Recompilation to Preventing Changes that Require Full Recompilation and revised figures.
2021.10.04 21.3
  • Updated Signal Tap Logic Analyzer Introduction with Signal Tap Logic Analyzer and Simulator Integration section.
  • Added description of Autorun mode to Managing Signal Tap Instances topic.
  • Added new Adding Simulator-Aware Signal Tap Nodes topic.
  • Added new Add Simulator Aware Node Finder Settings topic.
  • Added new Signal Tap and Simulator Integration topic.
  • Added new Generating a Simulation Testbench from Signal Tap Data topic.
  • Added new Create Simulation Testbench Dialog Box Settings topic.
  • Revised Preserving Signals for Monitoring and Debugging topic for latest techniques and links to other resources.
  • Revised Adding Pre-Synthesis or Post-Fit Nodes for latest techniques and links to other resources.
  • Added new Changing the Post-Fit Signal Tap Target Nodes topic.
  • Updated Adding Pre-Synthesis or Post-Fit Nodes topic for preserve for debug filters.
  • Added details about SOF Manager to Ensure Compatibility Between .stp and .sof Files topic.
2020.09.28 20.3
  • Revised "Signal Tap Logic Analyzer Introduction" for screenshot and details about role of Signal Tap Intel® FPGA IP.
  • Revised graphic and wording in "Signal Tap Hardware and Software Requirements" topic.
  • Revised wording and link to download in "Running the Stand-Alone Version of Signal Tap."
  • Updated flow diagram and added links to retitled "Signal Tap Debugging Flow" topic.
  • Retitled "Add the Signal Tap Logic Analyzer to Your Design" to "Step 1: Add the Signal Tap Logic Analyzer to the Project," and referenced new template and added links to next steps.
  • Added "Creating a Signal Tap Instance with the Signal Tap GUI" topic.
  • Added new "Signal Tap File Templates" topic.
  • Added new "Creating a Signal Tap Instance by HDL Instantiation" topic.
  • Added new "Signal Tap Intel® FPGA IP Parameters" topic.
  • Retitled "Configure the Signal Tap Logic Analyzer" to "Step 2: Configure the Signal Tap Logic Analyzer," and referenced new template and added links to next steps.
  • Enhanced description in Step 5: Run the Signal Tap Logic Analyzer" topic.
  • Revised "Adding Signals to the Signal Tap Logic Analyzer" to add detailed steps and screenshot.
  • Retitled and revised "Adding Nios® II Processor Signals" to reflect there is only one plug-in in Intel® Quartus® Prime Pro Edition.
  • Revised "Disabling or Enabling Signal Tap Instances" and added screenshot.
  • Replaced outdated links to AN446 with links to AN845.
  • Revised headings and steps in "Debugging Block-Based Designs with Signal Tap" section.
  • Retitled "Debugging Imported Snapshots" to "Compiler Snapshots and Signal Tap Debugging".
  • Retitled "Backward Compatibility" to "Signal Tap File Version Compatibility."
  • Removed incorrect statement about debugging multiple designs from "Step 4: Program the Target Hardware" topic.
  • Removed reference to obsolete resource checking function from "Ensure Compatibility Between STP and SOF Files" topic.
  • Removed obsolete "Remote Debugging Using the Signal Tap Logic Analyzer" section.
  • Removed obsolete "Estimating FPGA Resources" topic.
2019.06.11 18.1.0 Added more explanation to Figure 64 about continuous and input mode.
2019.05.01 18.1.0 In Adding Signals with a Plug-In topic, removed outdated information from step 1 about turning on Create debugging nodes for IP cores.
2018.09.24 18.1.0
  • Added content about debugging designs in block-based flows.
  • Renamed topic: Untappable Signals to Signals Unavailable for Signal Tap Debugging.
2018.08.07 18.0.0 Reverted document title to Debug Tools User Guide: Intel Quartus Prime Pro Edition.
2018.07.30 18.0.0 Updated Partial Reconfiguration sections to reflect changes in the PR flow.
2018.05.07 18.0.0
  • Added note stating Signal Tap IP not optimized for Stratix 10 Devices.
  • Moved information about debug fabric on PR designs to the System Debugging Tools Overview chapter.
  • Removed restrictions of Rapid Recompile support for Intel Stratix 10 devices.
2017.11.06 17.1.0
  • Added support for Incremental Routing in Intel Stratix 10 devices.
  • Removed unsupported FSM auto detection.
  • Clarified information about the Data Log Pane.
  • Updated Figure: Data Log and renamed to Simple Data Log.
  • Added Figure: Accessing the Advanced Trigger Condition Tab.
  • Removed outdated information about command-line flow.
2017.05.08 17.0.0
  • Added: Open Standalone Signal Tap Logic Analyzer GUI.
  • Added: Debugging Partial Reconfiguration Designs Using Signal Tap Logic Analyzer.
  • Updated figures on Create Signal Tap File from Design Instance(s).
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Added: Create SignalTap II File from Design Instance(s).
  • Removed reference to unsupported Talkback feature.
2016.05.03 16.0.0
  • Added: Specifying the Pipeline Factor
  • Added: Comparison Trigger Conditions
2015.11.02 15.1.0
  • Changed instances of Quartus II to Intel Quartus Prime.
  • Updated content to reflect SignalTap II support in Intel Quartus Prime Pro Edition
2015.05.04 15.0.0 Added content for Floating Point Display Format in table: SignalTap II Logic Analyzer Features and Benefits.
2014.12.15 14.1.0 Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
December 2014 14.1.0
  • Added MAX 10 as supported device.
  • Removed Full Incremental Compilation setting and Post-Fit (Strict) netlist type setting information.
  • Removed outdated GUI images from "Using Incremental Compilation with the SignalTap II Logic Analyzer" section.
June 2014 14.0.0
  • DITA conversion.
  • Replaced MegaWizard Plug-In Manager and Megafunction content with IP Catalog and parameter editor content.
  • Added flows for custom trigger HDL object, Incremental Route with Rapid Recompile, and nested groups with Basic OR.
  • GUI changes: toolbar, drag to zoom, disable/enable instance, trigger log time-stamping.
November 2013 13.1.0 Removed HardCopy material. Added section on using cross-triggering with DS-5 tool and added link to white paper 01198. Added section on remote debugging an Altera SoC and added link to application note 693. Updated support for MEX function.
May 2013 13.0.0
  • Added recommendation to use the state-based flow for segmented buffers with separate trigger conditions, information about Basic OR trigger condition, and hard processor system (HPS) external triggers.
  • Updated “Segmented Buffer” on page 13-17, Conditional Mode on page 13-21, Creating Basic Trigger Conditions on page 13-16, and Using External Triggers on page 13-48.
June 2012 12.0.0 Updated Figure 13–5 on page 13–16 and “Adding Signals to the SignalTap II File” on page 13–10.
November 2011 11.0.1 Template update.

Minor editorial updates.

May 2011 11.0.0 Updated the requirement for the standalone SignalTap II software.
December 2010 10.0.1 Changed to new document template.
July 2010 10.0.0
  • Add new acquisition buffer content to the “View, Analyze, and Use Captured Data” section.
  • Added script sample for generating hexadecimal CRC values in programmed devices.
  • Created cross references to Quartus II Help for duplicated procedural content.
November 2009 9.1.0 No change to content.
March 2009 9.0.0
  • Updated Table 13–1
  • Updated “Using Incremental Compilation with the SignalTap II Logic Analyzer” on page 13–45
  • Added new Figure 13–33
  • Made minor editorial updates
November 2008 8.1.0 Updated for the Quartus II software version 8.1 release:
  • Added new section “Using the Storage Qualifier Feature” on page 14–25
  • Added description of start_store and stop_store commands in section “Trigger Condition Flow Control” on page 14–36
  • Added new section “Runtime Reconfigurable Options” on page 14–63
May 2008 8.0.0 Updated for the Quartus II software version 8.0:
  • Added “Debugging Finite State machines” on page 14-24
  • Documented various GUI usability enhancements, including improvements to the resource estimator, the bus find feature, and the dynamic display updates to the counter and flag resources in the State-based trigger flow control tab
  • Added “Capturing Data Using Segmented Buffers” on page 14–16
  • Added hyperlinks to referenced documents throughout the chapter
  • Minor editorial updates

Did you find the information on this page useful?

Characters remaining:

Feedback Message