Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022
Public

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2.4.8.1. Input Port Mode

When using the Input port mode, the Signal Tap logic analyzer takes any signal from your design as an input. During acquisition, if the signal is high on the clock edge, the Signal Tap logic analyzer stores the data in the buffer. If the signal is low on the clock edge, the logic analyzer ignores the data sample. If you don't specify an internal node, the logic analyzer creates and connects a pin to this input port.

When creating a Signal Tap logic analyzer instance with the Signal Tap logic analyzer GUI, specify the Storage Qualifier signal for the Input port field located on the Setup tab. You must specify this port for your project to compile.

When creating a Signal Tap logic analyzer instance through HDL instantiation, specify the Storage Qualifier parameter to include in the instantiation template. You can then connect this port to a signal in your RTL. If you enable the input port storage qualifier, the port accepts a signal and predicates when signals are recorded into the acquisition buffer before or after the specified trigger condition occurs. That is, the trigger you specify is responsible for triggering and moving the logic analyzer into the post-fill state. The input port storage qualifier signal you select controls the recording of samples.

The following example compares and contrasts two waveforms of the same data, one without storage qualifier enabled (Continuous means always record samples, effectively no storage qualifier), and the other with Input Port mode. The bottom signal in the waveform, data_out[7],is the input port storage qualifier signal. The continuous mode waveform shows 01h, 07h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh, 10h as the sequence of data_out[7] bus values where the storage qualifier signal is asserted. The lower waveform for input port storage qualifier shows how this same traffic pattern of the data_out bus is recorded when you enable the input port storage qualifier. Values recorded are a repeating sequence of the 01h, 07h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh, 10h (same as Continuous mode).

Figure 64. Comparing Continuous and Input Port Capture Mode in Data Acquisition of a Recurring Data Pattern
  • Continuous Mode:
  • Input Port Storage Qualifier:

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