Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022
Public

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Document Table of Contents

2.4.6.5.1. Using the Custom Trigger HDL Object

To define a custom trigger flow:
  1. Select the trigger you want to edit.
  2. Open the Advanced Trigger tab by selecting Advanced in the Trigger Conditions list.
  3. Add to your project the Verilog HDL or VHDL source file that contains the trigger module using the Project Navigator.
  4. Implement the inputs and outputs that your Custom Trigger HDL module requires.
  5. Drag in your Custom Trigger HDL object and connect the object’s data input bus and result output bit to the final trigger result.
    Figure 48. Custom Trigger HDL Object
  6. Right-click your Custom Trigger HDL object and configure the object’s properties.
    Figure 49. Configure Object Properties
  7. Compile your design.
  8. Acquire data with Signal Tap using your custom Trigger HDL object.

Verilog HDL Triggers

The following trigger uses configuration bitstream:

module test_trigger
	(
		input acq_clk, reset,
		input[3:0] data_in,
		input[1:0] pattern_in,
		output reg trigger_out
	);
	always @(pattern_in) begin
		case (pattern_in)
			2'b00:
				trigger_out = &data_in;
			2'b01:
				trigger_out = |data_in;
			2'b10:
				trigger_out = 1'b0;
			2'b11:
				trigger_out = 1'b1;
		endcase
	end
endmodule

This trigger does not have configuration bitstream:

module test_trigger_no_bs
	(
		input acq_clk, reset,
		input[3:0] data_in,
		output reg trigger_out
	);
	assign trigger_out = &data_in;
endmodule

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