Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022
Public

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2.5.3.1. Increasing Signal Tap Logic Performance

If Signal Tap logic is part of your critical path, follow these tips to speed up the performance of the Signal Tap logic:

  • Disable runtime configurable options—runtime flexibility features expend some device resources. If you use Advanced Triggers or State-based triggering flow, disable runtime configurable parameters to a boost in fMAX of the Signal Tap logic. If you use the State-based triggering flow, disable the Goto state destination option and perform a recompilation before disabling the other runtime configurable options. The Goto state destination option has the greatest impact on fMAX, compared to the other runtime configurable options.
  • Minimize the number of signals that have Trigger Enable selected—By default, the Signal Tap logic analyzer enables the Trigger Enable option for all signals that you add to the .stp file. For signals that you do not plan to use as triggers, turn this option off.
  • Turn on Physical Synthesis for register retiming—If many (more than the number of inputs that fit in a LAB) enabled triggering signals fan-in logic to a gate-based triggering condition (basic trigger condition or a logical reduction operator in the advanced trigger tab), turn on Perform register retiming. This can help balance combinational logic across LABs.

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