Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022

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2.3.2. Creating a Signal Tap Instance by HDL Instantiation

You can create a Signal Tap Instance by HDL instantiation, rather than using the Signal Tap logic analyzer GUI. When you use HDL instantiation, you first parameterize and instantiate the Signal Tap Logic Analyzer Intel FPGA IP in your RTL. Next, you compile the design and IP, and run a Signal Tap analysis using the generated .stp file. Follow these steps to create a Signal Tap instance by HDL instantiation:
Signal Tap Logic Analyzer Intel FPGA IP
  1. From the Intel® Quartus® Prime IP Catalog (View > IP Catalog), locate and double-click the Signal Tap Logic Analyzer Intel FPGA IP.
  2. In the New IP Variant dialog box, specify the File Name for your Signal Tap instance, and then click Create. The IP parameter editor displays the available parameter settings for the Signal Tap instance.
  3. In the parameter editor, specify the Data, Segmented Acquisition, Storage Qualifier, Trigger, and Pipelining parameters, as Signal Tap Intel FPGA IP Parameters describes.
  4. Click Generate HDL. The parameter editor generates the HDL implementation of the Signal Tap instance according your specifications.
    Figure 24. IP Parameter Editor
  5. To instantiate the Signal Tap instance in your RTL, click Generate > Show Instantiation Template in the parameter editor. Copy the Instantiation Template contents into your RTL.
    Figure 25.  Signal Tap Logic Analyzer Intel FPGA IP Instantiation Template
  6. Run at least the Analysis & Synthesis stage of the Compiler to synthesize the RTL (including Signal Tap instance) by clicking Processing > Start > Start Analysis & Synthesis. Alternatively, you can run full compilation and the Assembler at this point if ready.
  7. When the Compiler completes, click Create/Update > Create Signal Tap File from Design Instance to create a .stp file for analysis in the Signal Tap logic analyzer GUI.
    Figure 26.  Create Signal Tap File from Design Instances Dialog Box
    Note: If your project contains partial reconfiguration partitions, the PR partitions display in a tree view. Select a partition from the view, and click Create Signal Tap file. The resulting .stp file that generates contains all HDL instances in the corresponding PR partition. The resulting .stp file does not include the instances in any nested partial reconfiguration partition.
  8. To analyze the Signal Tap instance, click File > Open and select the .stp file. The Signal Tap instance opens in the Signal Tap logic analyzer GUI for analysis. All the fields are read-only, except runtime-configurable trigger conditions.
  9. Modify any runtime-configurable trigger conditions, as Runtime Reconfigurable Options describes.