Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022
Public

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2.9.3.2.3. Preparing PR Personas for Signal Tap Debugging

Before you create revisions for personas in your design, you must instantiate debug IP components and tap signals.

For each PR persona that you want to debug:

  1. Instantiate the SLD JTAG Bridge Host Intel® FPGA IP in the PR persona.
  2. Tap pre-synthesis nodes in the PR persona only.
  3. Save in a new .stp file with a name that identifies the persona.
  4. Use the new .stp file in the implementation revision.
If you do not want to debug a particular persona, drive the tdo output signal to 0.

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