Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022
Public

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Document Table of Contents

6.7. Design Debugging Using In-System Sources and Probes Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2022.07.08 22.1
  • Fixed broken link in "Design Example: Dynamic PLL Reconfiguration".
2019.06.11 18.1.0 Rebranded megafunction to Intel® FPGA IP core
2018.05.07 18.0.0 Added details on finding the In-System Sources and Probes in the IP Catalog.
2016.10.31 16.1.0 Implemented Intel rebranding.
2015.11.02 15.1.0 Changed instances of Quartus II to Intel® Quartus® Prime .
June 2014 14.0.0 Updated formatting.
June 2012 12.0.0 Removed survey link.
November 2011 10.1.1 Template update.
December 2010 10.1.0 Minor corrections. Changed to new document template.
July 2010 10.0.0 Minor corrections.
November 2009 9.1.0
  • Removed references to obsolete devices.
  • Style changes.
March 2009 9.0.0 No change to content.
November 2008 8.1.0 Changed to 8-1/2 x 11 page size. No change to content.
May 2008 8.0.0
  • Documented that this feature does not support simulation on page 17–5
  • Updated Figure 17–8 for Interactive PLL reconfiguration manager
  • Added hyperlinks to referenced documents throughout the chapter
  • Minor editorial updates

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