Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022
Public

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2.4.5.2. Adding Simulator-Aware Signal Tap Nodes

Note: This version of the Signal Tap simulator integration feature is a beta release. The following known limitations apply to this beta release:
  • Supports only Verilog HDL simulation.
  • Supports testbench generation only within the current project directory.
To automatically generate and add a list of simulator-aware signals to the Signal Tap Node list for Signal Tap and simulator monitoring, follow these steps:
  1. To generate the pre-synthesis design netlist, click Processing > Start > Start Analysis & Elaboration.
  2. In the Signal Tap logic analyzer, click Edit > Add Simulator Aware Nodes. The Simulator Aware Node Finder opens, allowing you to specify the following options to find and add the minimum set of nodes to tap to for full visibility into the selected hierarchy's cone of logic:
    1. Click the Select Hierarchies button, select one or more design hierarchies that you want to tap, and then click OK. The clock domains in the hierarchy appear in the Clock Domains list.
    2. Under Clock Domains, enable only the domains of interest. If you select multiple clock domains, Signal Tap creates an instance for each domain.
    3. Click the Search button. All nodes required to provide full visibility into the selected hierarchy automatically appear enabled in the Total nodes to tap list. Disabling any of the simulator-aware nodes may reduce simulation visibility.
    4. Click the Insert button. The enabled signals in the Total nodes to tap list are copied to the Signal Tap Node list, and the acquisition clock updates according to the simulator-aware signal data. Refer to Add Simulator-Aware Node Finder Settings.
      Figure 35. Simulator Aware Node Finder
      Figure 36. Simulator-Aware Nodes Copied to Signal Tap Window
  3. Modify trigger conditions for the Signal Tap nodes, as Defining Trigger Conditions describes.
  4. Compile the design and Signal Tap instance, Step 3: Compile the Design and Signal Tap Instances describes.
  5. Program the target hardware, as Step 4: Program the Target Hardware describes.
  6. Run the Signal Tap logic analyzer, as Step 5: Run the Signal Tap Logic Analyzer describes.
  7. Generate a simulation testbench from Signal Tap capture data, as Generating a Simulation Testbench from Signal Tap Data describes.

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