Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022

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Document Table of Contents Debugging an Exported Root Partition and Core Partition Simultaneously using the SLD JTAG Bridge

When you reuse an exported root partition in another project, the exported .qdb includes the Signal Tap connection to signals in the root partition, and the SLD JTAG Bridge Agent IP, which allows debugging logic in the core partition.

To perform Signal Tap debugging in a project that includes a reused root partition:

  1. Add the exported .qdb (and .sdc) files to the project that reuses them.
  2. From the IP Catalog, parameterize and instantiate the SLD JTAG Bridge Host Intel® FPGA IP in the core partition.
  3. Run the Analysis & Synthesis stage of the Compiler.
  4. Create a Signal Tap instance in the core partition, as Step 1: Add the Signal Tap Logic Analyzer to the Project describes.
  5. In the Signal Tap instance, specify post-synthesis signals for monitoring.
    Note: You can only tap signals in the core partition.
  6. Compile the design and Signal Tap instance.
  7. Generate a Signal Tap file for the reused root partition with the quartus_stp command.
  8. Program the device.
  9. Perform hardware verification of the reserved core partition with the Signal Tap instance defined in Step 3.
  10. Perform hardware verification of the reused root partition with the Signal Tap instance defined in Step 7.

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