Intel® Quartus® Prime Pro Edition User Guide: Debug Tools

ID 683819
Date 7/08/2022
Public

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1.8.2.2.1. HDL Implementation

The recommended method of preserving nodes for debug is to add HDL pragmas or attributes to the design files.

Table 6 defines the preserve for debug pragma and .qsf assignment setting.

Table 6.  Preserve for Debug Pragma
Term Equivalent (.qsf) Setting Description
preserve_for_debug PRESERVE_FOR_DEBUG

Prevents the Fitter from optimizing away a register or combinational signal. The pragma also prevents any retiming, merging, and duplication optimization. This optimization prevention applies when the setting, PRESERVE_FOR_DEBUG_ENABLE is ON.

Add HDL pragmas to Verilog HDL design files in the following way:

(* preserve_for_debug *) reg my_reg;

Add HDL attributes to VHDL design files in the following way:

signal keep_wire : std_logic;
attribute keep: boolean;
attribute keep of keep_wire: signal is true;

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